1. Field of the Invention
The present invention is related to integrated circuit power consumption and more particularly to reducing static random access memory (SRAM) power consumption.
2. Background Description
Semiconductor technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). Generally, all other factors being constant, the active power consumed by a given unit increases linearly with switching frequency. Thus, not withstanding the decrease of chip supply voltage, chip power consumption has increased as well. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power. For low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, reducing net power consumption is important but, such a power reduction must come without degrading chip/circuit performance below acceptable levels.
To minimize semiconductor circuit power consumption, most integrated circuits (ICs) are made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS. A typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (modeled simply as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa. Thus, ideally, there is no static or DC current path in a typical CMOS circuit.
A CMOS inverter, for example, is a PFET and NFET pair that are series connected between a power supply voltage (Vdd) and ground (GND). Both are gated by the same input and both drive the same output, typically a capacitive load. The PFET pulls the output high and the NFET pulls the output low at opposite input signal states. Ideally, when the gate of a NFET is below some positive threshold voltage (VT) with respect to its source, the NFET is off, i.e., the switch is open. Above VT, the NFET is on conducting current, i.e., the switch is closed. Similarly, a PFET is off when its gate is above its VT, i.e., less negative, and on below VT. So, ideal CMOS circuits use no static or DC power and only consume transient power from charging and discharging capacitive loads.
In practice however, typical FETs are much more complex than switches and transient power for circuit loads accounts for only a portion of CMOS circuit power consumption. FET drain to source current (DC current and so, DC power consumed) is dependent upon circuit conditions and device voltages. Especially as FET features shrink, FETs conduct what is known as subthreshold current, i.e., at gate biases below threshold for NFETs and above for PFETs. Further, for a particular device, subthreshold current increases exponentially with the magnitude of the device's drain to source voltage (Vds) and reduces exponentially with the magnitude of the device's VT. This is especially true in what is known as partially depleted (PD) or fully depleted (FD) silicon on insulator (SOI) technologies, where subthreshold leakage has been shown to increase dramatically, such that it may be the dominant source of leakage. Additional device leakages including gate leakages (i.e., gate to channel, gate to source or drain and gate induced drain leakage (GIDL)) and source/drain junction leakages also contribute to static power.
When multiplied by the millions and even billions of devices on a state of the art IC, even 100 picoAmps (100 pA) of leakage in each of a million devices, for example, results in chip leakage on the order of 100 milliAmps (100 mA). Thus, as chip features have shrunk, these leakage sources have become more prominent. While increasing device VT (e.g., with thicker gate oxide or body biasing device channels) can reduce subthreshold leakage, typically, these leakage reduction techniques increase circuit size, e.g., to accommodate body contacts at devices and/or to compensate for worse (slower) circuit performance by devices with higher VTS. Generally, and especially with the large number of circuits and circuit devices on a particular chip, device leakage (both gate and subthreshold) reduction techniques have been applied uniformly across circuits or chips to reduce leakage power; accepting an across the board performance and/or chip density degradation, regardless of whether application of the particular technique affected leakage reduction for any particular circuit or circuit block.
Thus, there is a need for reduced IC leakage with minimal performance degradation and in particular for maximizing device off resistance while minimizing device on resistance, especially for PD and FD SOI ICs.